Warpage Simulation Study by Trace Mapping Method for FCCSP with ETS Substrate

Abstract ETS (Embedded trace substrate) has become as the mainstream substrate for FCCSP since it fine trace, better dimension control and low cost advantages which compared to normal substrate. But usually encountered more serious warpage issue bare complete package may influence D/B (die bonding) SMT yield rate due its coreless characteristic. Especially with special pattern design (ex. larger Copper area), appear peculiar contour led non-wetting at specific location during process. Thus, if can predict value accurately is an important topic. In this paper, a was chosen study impact. Bare simulation models w/ w/o considering by mapping method were performed shadow moiré results. Analysis results showed that could get accurate similar warpage.